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ds05-20842-4e fujitsu semiconductor data sheet embedded erase?, embedded program? and expressflash? are trademarks of advanced micro devices, inc. flash memory cmos 4m (512k 8) bit mbm29f040c -55/-70/-90 n features ? single 5.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard byte-wide pinouts 32-pin plcc (package suffix: pd) 32-pin tsop(i) (package suffix: pf) 32-pin tsop(i) (package suffix: pftn C normal bend type, pftr C reversed bend type) ? minimum 100,000 write/erase cycles ? high performance 55 ns maximum access time ? sector erase architecture 8 equal size sectors of 64k bytes each any combination of sectors can be concurrently erased. also supports full chip erase. ? embedded erase? algorithms automatically pre-programs and erases the chip or any sector ? embedded program? algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ?low v cc write inhibit 3.2 v ? sector protection hardware method disables any combination of sectors from write or erase operations ? erase suspend/resume suspends the erase operation to allow a read data in another sector within the same device
2 mbm29f040c -55/-70/-90 n pac k ag e marking side (lcc-32p-m02) (fpt-32p-m24 assembly: malaysia) (fpt-32p-m25 assembly: malaysia) marking side marking side 32-pin plastic qfj (plcc) 32-pin plastic tsop (i) 32-pin plastic tsop (i)
3 mbm29f040c -55/-70/-90 n general description the mbm29f040c is a 4m-bit, 5.0 v-only flash memory organized as 512k bytes of 8 bits each. the mbm29f040c is offered in a 32-pin plcc and 32-pin tsop(i) package. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29f040c offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29f040c is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 v flash or eprom devices. the mbm29f040c is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in less than 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. any individual sector is typically erased and verified in 1 second. (if already completely preprogrammed.) the device also features a sector erase architecture. the sector mode allows for 64k byte sectors of memory to be erased and reprogrammed without affecting other sectors. the mbm29f040c is erased when shipped from the factory. the device features single 5.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 or by the toggle bit feature on dq 6 . once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsu's flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability and cost effectiveness. the mbm29f040c memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection.
4 mbm29f040c -55/-70/-90 ? 64k byte per sector ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable 64k byte per sector 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h n flexible sector-erase architecture
5 mbm29f040c -55/-70/-90 n product line up n block diagram part no. mbm29f040c ordering part no. v cc = 5.0 v 5% -55 v cc = 5.0 v 10% -70 -90 max. address access time (ns) 55 70 90 max. ce access time (ns) 55 70 90 max. oe access time (ns) 30 30 35 v ss v cc we ce a 0 to a 18 oe erase voltage generator dq 0 to dq 7 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for program/erase
6 mbm29f040c -55/-70/-90 n connection diagrams a 11 a 9 a 8 a 13 a 14 a 17 we v cc a 18 a 16 a 15 a 12 a 7 a 6 a 5 a 4 oe a 10 ce dq 7 dq 6 dq 5 dq 4 dq 3 v ss dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 12 a 15 a 16 a 18 v cc we a 17 a 14 a 13 a 8 a 9 a 11 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss dq 3 dq 4 dq 5 dq 6 dq 7 ce a 10 oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 mbm29f040c standard pinout mbm29f040c reverse pinout tsop (i) a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 a 14 a 13 a 8 a 9 a 11 oe a 10 ce dq 7 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 4 3 2 1 32 31 30 14 15 16 17 18 19 20 dq 1 dq 2 v ss dq 3 dq 4 dq 5 dq 6 plcc a 12 a 15 a 16 a 18 v cc we a 17 lcc-32p-m02 fpt-32p-m24 fpt-32p-m25 marking side marking side
7 mbm29f040c -55/-70/-90 n logic symbol legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 5. 2. refer to the section on sector protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. table 1 mbm29f040c pin configuration pin function a 0 to a 18 address inputs dq 0 to dq 7 data inputs/outputs ce chip enable oe output enable we write enable v ss device ground v cc device power supply table 2 mbm29f040c user bus operations operation ce oe we a 0 a 1 a 6 a 9 i/o auto-select manufacturer code (1) l l h l l l v id code auto-select device code (1) l l h h l l v id code read (3) l l h a 0 a 1 a 6 a 9 d out standby hxxxxxxhigh-z output disable lhhxxxxhigh-z write (program/erase) l h l a 0 a 1 a 6 a 9 d in enable sector protection (2) l v id xxxv id x verify sector protection (2) l l h l h l v id code 19 a 0 to a 18 we oe ce dq 0 to dq 7 8
8 mbm29f040c -55/-70/-90 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29f040 c -55 pd device number/description mbm29f040 4mega-bit (512k 8-bit) cmos flash memory 5.0 v-only read, program, and erase 64k byte sectors package type pd =32-pin rectangular plastic leaded chip carrier (plcc) pftn = 32-pin thin small outline package (tsop) standard pinout pftr =32-pin thin small outline package (tsop) reverse pinout speed option see product selector guide c = device revision
9 mbm29f040c -55/-70/-90 n functional description read mode the mbm29f040c has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time). standby mode the mbm29f040c has two standby modes, a cmos standby mode (ce input held at v cc 0.3 v.), when the current consumed is less than 5 a; and a ttl standby mode (ce is held at v ih ) when the current required is reduced to approximately 1 ma. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = v ih . the device can be read with standard access time (t ce ) from either of these standby modes. in the standby mode the outputs are in a high impedance state, independent of the oe input. if the device is deselected during erasure or programming, the device will draw active current until the operation is completed. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 . (recommend v il for the other pins.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29f040c is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 5. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufactures code (fujitsu = 04h) and byte 1 (a 0 = v ih ) represents the device identifier code (mbm29f040c = a4h). these two bytes are given in the table 3. all identifiers for manufactures and device will exhibit odd parity with the msb (dq 7 ) defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see table 3.)
10 mbm29f040c -55/-70/-90 * : outputs 01h at protected sector addresses and 00h at unprotected sector addresses. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29f040c features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 8). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v) and ce = v ih . the sector addresses (a 18 , a 17 and a 16 ) should be set to the sector to be protected. table 4 defines the sector address for each of the eight (8) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 11 and 17 sector protection waveforms and algorithm. table 3 mbm29f040c sector protection verify autoselect codes type a 18 a 17 a 16 a 6 a 1 a 0 code (hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code xxxv il v il v il 04h00000100 device code x x x v il v il v ih a4h10100100 sector protection sector addresses v il v ih v il 01h*00000001 table 4 sector address tables sector address a 18 a 17 a 16 address range sa0 0 0 0 00000h to 0ffffh sa1 0 0 1 10000h to 1ffffh sa2 0 1 0 20000h to 2ffffh sa3 0 1 1 30000h to 3ffffh sa4 1 0 0 40000h to 4ffffh sa5 1 0 1 50000h to 5ffffh sa6 1 1 0 60000h to 6ffffh sa7 1 1 1 70000h to 7ffffh
11 mbm29f040c -55/-70/-90 to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 16 , a 17 and a 18 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 16 , a 17 and a 18 ) are the sector address will produce a logical 1 at dq 0 for a protected sector. see table 3 for autoselect codes. notes: 1. address bits a 11 to a 18 = x = h or l for all address commands except for program address (pa) and sector address (sa). 2. bus operations are defined in table 2. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , and a 16 will uniquely select any sector. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of we . *: either of the two reset commands will reset the device. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. table 5 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/ reset commands are functionally equivalent, resetting the device to the read mode. table 5 mbm29f040c command definitions command sequence read/reset bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset* 1 xxxh f0h read/reset* 4 555h aah 2aah 55h 555h f0h ra rd autoselect 3 555h aah 2aah 55h 555h 90h byte program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (h or l). data (b0h) sector erase resume erase can be resumed after suspend with addr (h or l). data (30h)
12 mbm29f040c -55/-70/-90 read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage (v id = 11.5 v to 12.5). however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h returns the device code a4h. (see table 3.) all manufacturer and device codes will exhibit odd parity with the msb (dq 7 ) defined as the parity bit. sector state (protection or unprotection) will be informed address xx02h. scanning the sector addresses (a 16 , a 17 , a 18 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see table 2 and 3.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program setup command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit (see write operation status section.) at which time the device returns to the read mode and addresses are no longer latched. (see table 6, hardware sequence flags.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device (exceed timing limits.), or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 13 illustrates the embedded program tm algorithm using typical command strings and bus operations.
13 mbm29f040c -55/-70/-90 chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. figure 14 illustrates the embedded erase algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector.) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . a time-out of 50 s from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s, otherwise that command will not be accepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to read mode, ignoring the previous command string. resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (1 to 7). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read mode. during the execution of the sector erase command, only the erase suspend and erase resume commands are allowed. all other commands will reset the device to read mode. data polling must be performed at an address within any of the sectors being erased. figure 14 illustrates the embedded erase tm algorithm using typical command strings and bus operations.
14 mbm29f040c -55/-70/-90 erase suspend the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which include the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 10 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
15 mbm29f040c -55/-70/-90 write operation status notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. 3. dq 0 and dq 1 are reserve pins for future use. dq 4 is for fujitsu internal use only. dq 7 data polling the mbm29f040c device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the device will produce the compliment of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 15. for chip erase, and sector erase the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29f040c data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out. (see table 6.) see figure 9 for the data polling timing specifications and diagrams. table 6 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program non-erase suspended sector) dq 7 toggle (note 1) 00 1 (note 2) exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 program/erase in embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
16 mbm29f040c -55/-70/-90 dq 6 toggle bit i the mbm29f040c also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see figure 10 for the toggle bit timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in table 2. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit i are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command. dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. refer to table 6: hardware sequence flags.
17 mbm29f040c -55/-70/-90 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: notes: 1. these status flags apply when outputs are read from a sector that has been erase-suspended. 2. these status flags apply when outputs are read from the byte address of the non-erase suspended sector. data protection the mbm29f040c is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. mode dq 7 dq 6 dq 2 program dq 7 toggles 1 erase 0 toggles toggles erase suspend read (erase-suspended sector) (note 1) 1 1 toggles erase suspend program dq 7 (note 2) toggles 1 (note 2)
18 mbm29f040c -55/-70/-90 power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
19 mbm29f040c -55/-70/-90 n absolute maximum ratings storage temperature .................................................................................... C55c to +125c ambient temperature with power applied .................................................... C40c to +85c voltage with respect to ground all pins except a 9 , oe (note 1).................. C2.0 v to +7.0 v v cc (note 1) .................................................................................................. C2.0 v to +7.0 v a 9 , oe (note 2) ............................................................................................. C2.0 v to +13.5 v notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 and oe pins are C0.5 v. during voltage transitions, a 9 and oe pins may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 and oe pins are +13.5 v which may overshoot to 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges ambient temperature (t a ) ................................................................................ C40c to +85c v cc supply voltages mbm29f040c-55.......................................................................................... +4.75 v to +5.25 v mbm29f040c-70/-90 ................................................................................... +4.50 v to +5.50 v operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
20 mbm29f040c -55/-70/-90 n maximum overshoot figure 1 maximum negative overshoot waveform +0.8 v C0.5 v 20 ns C2.0 v 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns figure 3 maximum positive overshoot waveform 2 * : this waveform is applied for a 9 , oe .
21 mbm29f040c -55/-70/-90 n dc characteristics notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz, with oe at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. applicable to sector protection function. 4. (v id C v cc ) do not exceed 9 v. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max 1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i lit a 9 , oe input leakage current v cc = v cc max., a 9 , oe = 12.0 v 50 a i cc1 v cc active current (note 1) ce = v il , oe = v ih 30ma i cc2 v cc active current (note 2) ce = v il , oe = v ih 45ma i cc3 v cc current (standby) v cc = v cc max., ce = v ih 1ma v cc = v cc max., ce = v cc 0.3 v 5 a v il input low level C0.5 0.8 v v ih input high level 2.0 v cc +0.3 v v id voltage for autoselect and sector protection (a 9 , oe ) (note 3, 4) v cc = 5.0 v 11.5 12.5 v v ol output low voltage level i ol = 12.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage level i oh = C2.5 ma, v cc = v cc min 2.4 v v oh2 i oh = C100 a v cc C0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
22 mbm29f040c -55/-70/-90 n ac characteristics ? read only operations characteristics note: 1. test conditions: output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -55 (note1) -70 (note2) -90 (note2) unit jedec standard t avav t rc read cycle time min. 55 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max. 55 70 90 ns t elqv t ce chip enable to output delay oe = v il max. 55 70 90 ns t glqv t oe output enable to output delay max. 30 30 35 ns t ehqz t df chip enable to output high-z max. 20 20 20 ns t ghqz t df output enable to output high-z max. 20 20 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min.0 0 0 ns figure 4 test conditions c l 5.0 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w note: 1.c l = 30 pf including jig capacitance 2.c l = 100 pf including jig capacitance note: 2. test conditions: oput load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level input: 0.8 and 2.0 v output: 0.8 and 2.0 v
23 mbm29f040c -55/-70/-90 ? write/erase/program operations notes: 1. this does not include the preprogramming time. 2. this timing is only for sector protect operations. parameter symbols description mbm29f040c unit jedec standard -55 -70 -90 t avav t wc write cycle time min. 55 70 90 ns t avwl t as address setup time min. 0 0 0 ns t wlax t ah address hold time min. 40 45 45 ns t dvwh t ds data setup time min. 25 30 45 ns t whdx t dh data hold time min. 0 0 0 ns t oes output enable setup time min. 0 0 0 ns t oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t ghel t ghel read recover time before write min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 30 35 45 ns t eleh t cp ce pulse width min. 30 35 45 ns t whwl t wph write pulse width high min. 20 20 20 ns t ehel t cph ce pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation typ. 8 8 8 s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 sec max. 8 8 8 sec t vcs v cc setup time min. 50 50 50 s t vlht voltage transition time (notes 2) min. 4 4 4 s t wpp write pulse width (note 2) min. 100 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 4 s t csp ce setup time to we active (note 2) min. 4 4 4 s t eoe delay time from embedded output enable max. 30 30 35 ns
24 mbm29f040c -55/-70/-90 n switching waveforms ? key to switching waveforms figure 5 ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance off state we oe ce t acc t df t oh t ce t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh
25 mbm29f040c -55/-70/-90 figure 6 ac waveforms for alternate we controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t ghwl t wp t df t ds t whwh1 t wc t ah 5.0v ce oe t rc addresses data t as t oe t wph t cs t dh dq 7 pd a0h d out t ce we 555h pa pa t oh data polling 3rd bus cycle t ch d out
26 mbm29f040c -55/-70/-90 figure 7 ac waveforms for alternate ce controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t ghel t cp t ds t whwh1 t wc t ah 5.0v we oe addresses data t as t cph t ws t dh dq 7 pd a0h d out ce 555h pa pa data polling 3rd bus cycle t wh
27 mbm29f040c -55/-70/-90 figure 8 ac waveforms chip/sector erase operations * : sa is the sector address for sector erase. addresses = 555h for chip erase t ghwl t ds v cc ce oe addresses data t dh we t ah 2aah 555h 555h 2aah sa * t wph t cs t wp t vcs t as 555h aah 55h 80h aah 55h 10h/30h t ch
28 mbm29f040c -55/-70/-90 figure 9 ac waveforms for data polling during embedded algorithm operations * : dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we t df t ch t ce high- z dq 7 = valid data dq 0 to dq 6 = output flag dq 0 to dq 6 t eoe dq 7 high- z valid data * dq 7 dq 0 to dq 6 data data figure 10 ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation). t oeh ce we oe dq 6 dq 6 = toggle * t oes t oe dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 valid data
29 mbm29f040c -55/-70/-90 figure 11 ac waveforms for sector protection timing diagram t vlht sax : sector address for initial sector sax a 18 a 17 a 16 say a 0 a 1 a 9 v id 5v t vlht oe v id 5v t vlht t oesp t wpp we ce t oe 01h data say : sector address for next sector a 6 a 2 to a 5 a 7 to a 18 t csp t vlht t vcs v cc
30 mbm29f040c -55/-70/-90 figure 12 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector. dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe
31 mbm29f040c -55/-70/-90 figure 13 embedded program tm algorithm embedded algorithms no yes program command sequence (address/command) 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? programming completed program address/program data start
32 mbm29f040c -55/-70/-90 figure 4 embedded erase tm algorithm embedded algorithms start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit successfully completed erasure completed chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h
33 mbm29f040c -55/-70/-90 figure 5 data polling algorithm note: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. fail dq 7 = data ? no no dq 7 = data ? dq 5 = 1? pass yes yes yes no start read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va
34 mbm29f040c -55/-70/-90 figure 6 toggle bit algorithm note: dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1. fail dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? pass yes no no yes start read byte (dq 0 to dq 7 ) read byte (dq 0 to dq 7 ) addr. = h or l addr. = h or l
35 mbm29f040c -55/-70/-90 figure 7 sector protection algorithm setup sector addr. (a 18 , a 17 , a 16 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes no oe = v id , a 9 = v id , ce = v il time out 100 m s read from sector addr. = sa, a 0 = 0, a 1 = 1, a 6 = 0 remove v id from a 9 write reset command increment plscnt no yes protect another sector ? start sector protection completed data = 01h? no yes plscnt = 25? remove v id from a 9 write reset command plscnt = 1 device failed
36 mbm29f040c -55/-70/-90 n erase and programming performance n tsop(i) pin capacitance note: test conditions t a = 25c, f = 1.0 mhz n plcc pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 8 sec excludes 00h programming prior to erasure byte programming time 8 150 s excludes system-level overhead chip programming time 4.2 10 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7 8 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 10 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7 8 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 10 pf
37 mbm29f040c -55/-70/-90 n package dimensions (continued) +0.05 C0.02 +.002 C.001 index 0.10(.004) 0.20 .008 (.410.020) 10.410.51 typ 0.66(.026) typ 0.43(.017) ref 10.16(.400) 7.62(.300)ref (.050.005) 1.270.13 typ r0.95(.037) (.510.020) 12.950.51 (.134.006) 3.400.16 (.089.015) 2.250.38 min 0.64(.025) (.588.005) 14.940.13 (.550.003) 13.970.08 (.487.005) 12.370.13 (.450.003) 11.430.08 14 20 29 21 13 5 30 32 4 1 1994 fujitsu limited c32021s-2c-4 c dimensions in mm(inches) 32-pin plastic qfj(plcc) (lcc-32p-m02)
38 mbm29f040c -55/-70/-90 (continued) +0.10 C0.05 +.004 C.002 0.25(.010) 0.15(.006) 0.15(.006) max 0.35(.014) max details of "a" part 1.10 .043 (stand off) 0.05(.002)min (.315.008) 8.000.20 typ 0.50(.0197) 0.10(.004) m ref. 7.50(.295) (.008.004) 0.200.10 (.006.002) 0.150.05 (.020.004) 0.500.10 0.10(.004) (.748.008) 19.000.20 (.724.008) 18.400.20 (.787.008) 20.000.20 lead no. "a" index 17 16 32 1 1994 fujitsu limited f32035s-2c-1 c (mounting height) dimensions in mm(inches) 32-pin plastic tsop(i) (fpt-32p-m24)
39 mbm29f040c -55/-70/-90 (continued) c 1997 fujitsu limited f32036s-2c-2 1 32 16 17 "a" lead no. 19.000.20 (.748.008) 0.10(.004) 20.000.20 (.787.008) 18.400.20 (.724.008) 0.150.05 (.006.002) 0.500.10 (.020.004) 8.000.20 (.315.008) 7.50(.295) ref. 0.200.10 (.008.004) 0.50(.0197) typ m 0.10(.004) 0.05(.002)min (stand off) .043 ?.002 +.004 ?0.05 +0.10 1.10 0.25(.010) 0.15(.006) 0.15(.006) max 0.35(.014) max details of "a" part index (mounting height) dimensions in mm(inches) 32-pin plastic tsop(i) (fpt-32p-m25)
40 mbm29f040c -55/-70/-90 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9903 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inhereut chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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